1. Field of the Invention
The present invention generally relates to an image processing apparatus and a processing method thereof, and more particularly to an image processing apparatus capable of performing spatial/temporal noise reduction and a processing method thereof.
2. Description of Related Art
The sophisticated advancement of the multimedia technology leads to an increasingly high requirement for high definition images at present. The quality of an image is highly correlated to noises concomitantly generated in image capturing, and signal transformation and transmission. In order to effectively reduce the noises to improve the image quality, more and more attentions are paid to the research of reduction of noises in the filed of image processing.
FIG. 1 is a block diagram of a conventional image processing apparatus 100. Referring to FIG. 1, an image capturing module 110 is used for capturing Bayer pattern images, and then the Bayer pattern images are corrected by a Vertical Distortion Correction (VDC) module 120 to compensate the vertical distortion. Subsequently, an Image Reproduce Pipeline (IRP) module 130 transforms the Bayer pattern images into YCbCr format images, and then transfers the transformed YCbCr format images to a geometric transform module 140 to perform geometric compensation so as to correct the problem of distortion caused by a lens in capturing of the images. Because image distortion is easily caused by shaking or quiver of the hand in the capturing of the images, the YCbCr format images are decreased in size by a scaling module 150, and then an image stabilization module 160 performs motion estimation and motion correction by using decreased Y channel images and originally sized Y channel images. Finally, a 2-dimensional noise reduction module 170 performs 2-dimensional spatial noise reduction on each image, to produce images which can be stored or played.
Images Img1˜Img5 as shown in FIG. 1 represent that at a position between different modules, the images must be stored by a Dynamic Random Access Memory (DRAM) for being processed by a Central Processing Unit (CPU) through operation. However, the capacity of the DRAM of the image processing apparatus 100 is limited, and thus for the architecture of the image processing apparatus 100 as shown in FIG. 1, most of the capacity of the DRAM is occupied, so that the conventional image processing apparatus 100 cannot accommodate other processing modules.